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XE1205
Figure 16 shows the read sequence of a single register:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
MOSI
start
rw
A(4)
A(3) A(2) A(1) A(0) stop
MISO
HZ
X
X
X
X
X
X
X
X
D(7) D(6) D(5) D(4) D(3) D(2) D(1)
D(0)
HZ
NSS_CONFIG
Figure 16: Read sequence of a single register via the SPI _CONFIG
7.1.2
Data transmission and reception via SPI_DATA interface.
When the transceiver is used in buffered mode, the data exchange with a micro-controller is done via the SPI_DATA
interface.
In transmit mode the16 byte FIFO can be filled as long as it is not full (IRQ_1 can be used if FIFO_full is mapped).
In receive mode, the FIFO may be read if one of the following events occurs:
?
?
?
at least one byte is present in the FIFO, i.e. a rising edge on IRQ_0 mapped to /fifoempty
each time a byte is written to FIFO, i.e. a rising edge on IRQ_0 mapped to WRITE_BYTE
16 bytes have been written to the FIFO, i.e. a rising edge on IRQ_1 mapped to RX_FIFOfull
The transceiver should be in buffered mode (MCParam_Buffered_mode = ‘1’). The SPI_DATA interface is then selected
if NSS_DATA is low and NSS_CONFIG is high.
The operations with SPI_DATA interface are similar to those with SPI_CONFIG except that there is only a data byte (no
address byte is required) and except that it is necessary to toggle the NSS_DATA signal back to high and back to low
between each transmitted or received byte.
? Semtech 2008
26
www.semtech.com
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